By Ahmed Amine Jerraya, Sungjoo Yoo, Norbert Wehn, Diederik Verkest
This name covers all software-related elements of SoC layout, from embedded and application-domain particular working structures to method structure for destiny SoC. it's going to provide embedded software program designers necessary insights into the restrictions imposed via embedded software program in an SoC context.
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It first requires the determination of worst and best case numbers for cache hits and misses‚ before cache influence on execution time can be calculated. The basic-block based timing analysis suffers from the over-conservative assumption of an unknown cache state at the beginning of each basic block. Formal Methods for Integration of Automotive Software 17 Therfore‚ in  a modified control-flow graph is proposed capturing potential cache conflicts between instructions in different basic blocks.
The lowest one‚ the system layer consists of the RTOS‚ typically based on the OSEK  automotive RTOS standard‚ and basic I/O. The system layer is usually provided by an RTOS vendor. The next upward level is the so-called ‘basic software’ which is added by the ECU vendor. It consists of standard functions that are specific to the role of the ECU. Generally speaking‚ with properly calibrated parameters‚ an ECU with RTOS and basic software is a working control unit for its specific automotive role.
Thus‚ we obtained measurements for an ‘always hit’ scenario for each analyzed segment. An alternative would be to use cycle-accurate core and cache simulators and pre-load the cache appropriately. However‚ such simulators were not available to us‚ and the SPR proved a convenient workaround. Next‚ we used a (non cycle-accurate) instruction set simulator to generate the corresponding memory access trace for each segment. This trace was then fed into the DINERO  cache simulator to determine the worst and best case ‘hit/miss scenarios’ that would result if the code was executed from external memory with real caching enabled.